Path: utzoo!attcan!uunet!husc6!rutgers!sunybcs!sher
From: sher@sunybcs.uucp (David Sher)
Newsgroups: comp.arch
Subject: Re: VLIW
Message-ID: <2828@cs.Buffalo.EDU>
Date: 23 Nov 88 03:17:19 GMT
References: <70@armada.UUCP> <28200237@urbsdc>
Sender: nobody@cs.Buffalo.EDU
Reply-To: sher@wolf.UUCP (David Sher)
Organization: SUNY/Buffalo Computer Science
Lines: 11

This is just an idea that has been floating around my mind for some time.
The CMU (and now perhaps GE) WARP is an MIMD systolic array full of 
powerful pipelined processors.  Its microinstruction set is designed to be
as orthogonal as possible.  So is the WARP a good candidate for VLIW 
techniques.  The architecture is a bit regular for such but that may not
be a disadvantage.  I was considering doing some research that a ways myself
but I find myself too busy to do that for a few years.
-David Sher
-David Sher
ARPA: sher@cs.buffalo.edu	BITNET: sher@sunybcs
UUCP: {rutgers,ames,boulder,decvax}!sunybcs!sher