Path: utzoo!attcan!uunet!husc6!ukma!uflorida!beach.cis.ufl.edu!seeger
From: seeger@beach.cis.ufl.edu (F. L. Charles Seeger III)
Newsgroups: comp.arch
Subject: Re: Gates vs Transistors (was: Some facts about the Acorn RISC Machine)
Keywords: Acorn RISC ARM
Message-ID: <19334@uflorida.cis.ufl.EDU>
Date: 23 Nov 88 05:27:08 GMT
References: <543@acorn.UUCP> <18267@ames.arc.nasa.gov> <19323@uflorida.cis.ufl.EDU> <18574@ames.arc.nasa.gov>
Sender: news@uflorida.cis.ufl.EDU
Reply-To: seeger@beach.cis.ufl.edu (F. L. Charles Seeger III)
Organization: UF EE Dept
Lines: 57

In article <19323@uflorida.cis.ufl.EDU> I wrote:
|>I can't speak much about real world practice, but can give a brief
|>background, since no one else has answered publicly.  Of course, counting
|>these things is a bit open to interpretation, e.g. what is a typical
|>gate? how to count a PLA or memory cell? etc.  I prefer to count

In article <18574@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) writes:
|Well, what I am really driving at is "4 input nand gate equivalents".
|(Or 2 input nand gate equivalents, if that makes more sense...)

It doesn't necessarily make any more sense, but "equivalent 2-input
nand gates" has been used, at least by some ASIC vendors.

|The reason is just that there is no convenient way to judge CPU
|complexity by "number of transistors" without knowing a lot about the
|technology.  I am looking for a ROUGH estimate of complexity independent
|of the number of transistors.
|
|I may be wrong, but may guess is that there is some easy and CONSISTENT
|way to measure CPU complexity which is ROUGHLY correct (within a factor
|of two).  Am I the only person out there wondering how much logic can be
|packed onto one of those new GaAs micros, and would like to compare that
|to a uVAX or MIPS chip?

Modulo 2, transistor count may be as good as anything, especially if you
account for the technology.  It is certainly easier to make this count
than that of gates, though we should restrict ourselves to counting
logic gates/transistors to measure complexity, i.e. not drive inverters/
transistors.  We might want to count memory/register cells separately.
If roughness is OK, the number of transistors in an N-input gate rarely
fall outside the (1.25-2.0)*N range.

The only other way to make this measurement, that springs to my feeble
mind, is to do some sort of analysis of the logic equations and state
machines (automata, for you CS guys) that are implemented.  I won't 
even think about trying to measure the dynamic complexity of the chip,
though this is probably the most important.  However, this sort of
approach is open to the same problems as regular benchmarking.  It
certainly wouldn't be "easy and CONSISTENT."  Then again, I only
vaguely have an idea as to what complexity is.  If I don't know how
to measure it ...

|Since this isn't going to be of use to
|marketeers, a simple measure which is USUALLY only slightly misleading
|would be of use.

If many people start quoting it, the marketeers will, too.  Transistor
counts used to be mentioned as new microprocessors were introduced.  It's
probably progress to quote MIPS/dhrystones per buck rather than the
gate count (i.e. the dynamic utility vs. static existence).  Either way,
there's a lot more to life than can be stuffed into a checksum.

Regards
--
  Charles Seeger            216 Larsen Hall
  Electrical Engineering    University of Florida
  seeger@iec.ufl.edu        Gainesville, FL 32611