Path: utzoo!attcan!uunet!convex!killer!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!pasteur!ucbvax!decwrl!armada!ian
From: ian@armada.UUCP (Ian L. Kaplan)
Newsgroups: comp.arch
Subject: Re: VLIW
Summary: The Warp already has a compiler that uses VLIW techniques
Message-ID: <74@armada.UUCP>
Date: 23 Nov 88 17:37:42 GMT
References: <70@armada.UUCP> <28200237@urbsdc> <2828@cs.Buffalo.EDU>
Organization: MassPar Inc., Santa Clara, CA
Lines: 35

In article <2828@cs.Buffalo.EDU>, sher@sunybcs.uucp (David Sher) writes:
> This is just an idea that has been floating around my mind for some time.
> The CMU (and now perhaps GE) WARP is an MIMD systolic array full of 
> powerful pipelined processors.  Its microinstruction set is designed to be
> as orthogonal as possible.  So is the WARP a good candidate for VLIW 
> techniques.  The architecture is a bit regular for such but that may not
> be a disadvantage.  I was considering doing some research that a ways myself
> but I find myself too busy to do that for a few years.


  The Warp has a compiler for a CMU developed language named W2.  This
  compiler does, in fact, use some VLIW techniques.  The work on the compiler
  was done by Monica Lam, Thomas Gross and their colleagues.  It is
  described in Dr. Lam's Phd thesis (A Systolic Array Optimizing Compiler
  Monica Sin-Ling Lam, May 1987, CMU-CS-87-187). 

  The Warp is an interesting machine, but its technology is several years old.
  CMU is working with iNTEL on a next generation machine, known as the iWarp.
  Last I heard, the iWarp would be a parallel processor with 72 PEs, arranged
  in a grid (I was tempted to write 2-D systolic array here, but just as
  the original Warp is much more flexible than a simple pipeline systolic
  array, the iWarp will be much more flexible than a simple 2-D systolic 
  array).  I expect that some interesting work on parallel programming 
  languages and environments will arise out of the iWarp project.  My guess
  is that there may end up being some similarities between the languages used
  to program the iWarp and the languages that are (or could be) used to
  program the Connection Machine.

  As far as work on VLIW, I would start soon, if I were you.  RISC is passe'.
  The next high performance microprocessor architecture will be VLIW.

                               Ian Kaplan
                               MassPar Inc.
 
                    I speak for myself and no one else.