Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!agate!bionet!apple!rutgers!deimos!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Gates vs Transistors (was: Some
Message-ID: <28200242@mcdurb>
Date: 25 Nov 88 21:03:00 GMT
References: <19334@uflorida.cis.ufl.EDU>
Lines: 28
Nf-ID: #R:uflorida.cis.ufl.EDU:19334:mcdurb:28200242:000:1559
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Nov 25 15:03:00 1988


|The reason is just that there is no convenient way to judge CPU
|complexity by "number of transistors" without knowing a lot about the
|technology.  I am looking for a ROUGH estimate of complexity independent
|of the number of transistors.
|
|I may be wrong, but may guess is that there is some easy and CONSISTENT
|way to measure CPU complexity which is ROUGHLY correct (within a factor
|of two).  Am I the only person out there wondering how much logic can be
|packed onto one of those new GaAs micros, and would like to compare that
|to a uVAX or MIPS chip?

One of the trade mags (I think it's VLSI Design) is flogging a set
of "benchmark circuits". The idea is that you take, say, MSI components,
and then see how many devices and how much area it takes to implement
that component in a given technology. The purpose is mainly to compare
gate arrays and not-quite-full-custom logic families -- in gate arrays
especially, the way in which the manufacturer lays the array out
can make a great difference in how costly it is to implement a
given function.  It may be possible to customize these benchmarks
in order to compare full-custom technologies.

Andy "Krazy" Glew   aglew@urbana.mcd.mot.com   uunet!uiucdcs!mcdurb!aglew
   Motorola Microcomputer Division, Champaign-Urbana Design Center
	   1101 E. University, Urbana, Illinois 61801, USA.
   
My opinions are my own, and are not the opinions of my employer, or
any other organisation. I indicate my company only so that the reader
may account for any possible bias I may have towards our products.