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From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: VLIW
Message-ID: <3684@pt.cs.cmu.edu>
Date: 26 Nov 88 02:57:17 GMT
References: <70@armada.UUCP> <28200228@urbsdc> <5087@mit-vax.LCS.MIT.EDU> <556@m3.mfci.UUCP> <5097@mit-vax.LCS.MIT.EDU> <3588@pt.cs.cmu.edu>
Organization: Carnegie-Mellon University, CS/RI
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I've had trouble responding to inquiries by mail, so, a posting.
The study that simulated a Cray-1 with Tomasulo interlocks was:

"Instruction Issue Logic for High-Performance Interruptable
Pipelined Processors", 14th Annual Int'l Symposium on Computer
Architecture (also Computer Arch. News vol.15 #2 June 1987) P.27

The original:
"An Efficient Algorithm For Exploiting Multiple Arithmetic Units",
R. Tomasulo, IBM Journal of R&D Jan 1967, p. 25
-- 
Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science
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