Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!amdahl!uunet!mcvax!enea!kth!draken!liuida!pausv
From: pausv@smidefix.liu.se (Paul Svensson)
Newsgroups: comp.arch
Subject: Re: penalty for microcode
Message-ID: <1073@smidefix.liu.se>
Date: 25 Nov 88 12:07:05 GMT
References: <3290@ucdavis.ucdavis.edu> <28200241@urbsdc>
Organization: CSG Lysator, Univ of Linkoping, Sweden
Lines: 29

In article <28200241@urbsdc> aglew@urbsdc.Urbana.Gould.COM writes:
>
>Cycles are a bad thing! The universe is not discrete.
>All instructions should be self-timed, to precisely the length of
>time required to do the operation.
>
>:-)


Hear, hear!

I couldn't resist following up on this one, since we actually have such a
beast down in the basement.  The FCPU (Flexible CPU), built by DataSAAB in the
early seventies is completely asynchronous.  The control units delivers
instructions to various computation modules, including main memory, which then
runs until ready.  Communication between modules are through "validated
registers" (queues of length one), because the control unit does not await
completion of an instruction before starting the next one.

It's a truly amazing machine.  At the moment we're running a FORTH in the
control unit only, with the rest of the machine, including main memory,
powered off.  But just wait 'til next week, when we've had cooling installed!
				:-)

DataSAAB couldn't sell more then about half a dozen of it, I guess partly
because they never used it to full capacity. They only used it to emulate
their previous design, a conventional mid-sixties mainframe. :-(
---
		Paul Svensson		psv@ida.liu.se