Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!mit-eddie!killer!aimania
From: aimania@killer.DALLAS.TX.US (Walter Rothe)
Newsgroups: comp.sys.amiga.tech
Subject: Re: 32-bit LUCAS memory board
Message-ID: <6236@killer.DALLAS.TX.US>
Date: 27 Nov 88 02:35:32 GMT
References: <1988Nov23.104910.15213@gpu.utcs.toronto.edu>
Organization: The Unix(R) Connection, Dallas, Texas
Lines: 49



 Brad, one thing you might want to consider is making is upwards compatible
 to a redesigned Lucas board with a 68030. The 68030 is capable of one
 clock updates when loading the cache. If you allowed page mode accesses
 when fetching sequential locations the board would have a longer life.
 These faster accesses could also help with a faster 68020.

 There are several observations/questions I had when a reviewed your
 board as an aid to my own design work.

 1) Dont you need a pullup resistor on AS00-.

 2) Why shut off AS going to the Amiga during a coprocessor cycle. Nothing
    should respond. Wouldnt it eliminate alot of the grant circuitry
    if you did not shut if off? Why is the flip flop needed to generate Z2-.

 3) Is there any problem caused by not buffering the address and data lines
    to the memory board. It seems like the length of the cable could cause
    reflections and crosstalk.

 4) Why are the two flip flops in series needed for BGACK?

 5) You mention in the article that DTPRELIM should have the same timing
    as C1 high C3 low and that your circuit does this. It may or may not
    do this depending on what state U9 comes up in and whether it is
    synchronized with the Amiga. If it comes up synced, it should stay
    synced though. This could be your parts selection problem. Depending
    on the part you select, you will eventually get one that powers up
    right.

 6) What does the extra buffer generating BUFOUT do? Does it prevent a
    race condition between the D and clock inputs of U11?

 7) I dont understand how the 68K, in a standard Amiga, gets synced with
    C1-C4 so that it doesnt put out an address strobe when C2 and C4 are
    high. Does DTACK from accesses to standard memory come at a certain
    time so that it gets synced with that. If there were only fast memory
    in a system, would it ever get synced?


 By the way, whats the going rate and minimum lot size these days for a
 board like yours? Was it alot of hassle?

 One final question. Has someone got your board to fit into the 2000?

-- 
Walter Rothe at the UNIX(Tm) Connection, Dallas, Tx
UUCP: {rutgers}!smu.killer.aimania