Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!cbmvax!grr
From: grr@cbmvax.UUCP (George Robbins)
Newsgroups: comp.sys.amiga.tech
Subject: Re: 32-bit LUCAS memory board
Message-ID: <5324@cbmvax.UUCP>
Date: 27 Nov 88 17:42:12 GMT
References: <1988Nov23.104910.15213@gpu.utcs.toronto.edu> <6236@killer.DALLAS.TX.US>
Reply-To: grr@cbmvax.UUCP (George Robbins)
Organization: Commodore Technology, West Chester, PA
Lines: 47

In article <6236@killer.DALLAS.TX.US> aimania@killer.DALLAS.TX.US (Walter Rothe) writes:
> 
>  There are several observations/questions I had when a reviewed your
>  board as an aid to my own design work.
> 
>  2) Why shut off AS going to the Amiga during a coprocessor cycle. Nothing
>     should respond. Wouldnt it eliminate alot of the grant circuitry
>     if you did not shut if off? Why is the flip flop needed to generate Z2-.

Please, the Amiga expansion bus is a basically and extension of the 68000
processor lines with a system implementation that ignores the FC lines.
Any cycles that can't be interpreted as memory cycles, (i.e. coprocessor
cycles) must be hidden from the system/bus by supressing address strobe.
Some 68020 adapters have neglected this detail, leading to less than
reliable operation...
> 
> 
>  7) I dont understand how the 68K, in a standard Amiga, gets synced with
>     C1-C4 so that it doesnt put out an address strobe when C2 and C4 are
>     high. Does DTACK from accesses to standard memory come at a certain
>     time so that it gets synced with that. If there were only fast memory
>     in a system, would it ever get synced?

There are two levels of synchronization.  First, the relation of the 7MHz
processor cycles vs. the 3.58 Mhz memory cycle - for this, AS is clocked
and DTACK asserted synchronous with the 3.58 MHz clocks so that the CPU
just gets and extra wait state anytime it ends up on and odd cycle.  Second,
the relation between "processor" and "chip/video" side cycles - this is
actually a bit weaker, whenever the processor tries to compete with the
chips for memory access, it loses.  Assuming memory bound operation, it
will tend to alternate cycles without extra wait states being needed,
however this is enforced more by the sequencing of chip and video refresh
cycles than any direct means.  For amusement, it is worth noting that
the "processor side" and "chip side" flip each line so that the processor
is apt to run on the "chip side" until the first video fetch or other
chip activity.

Note that some memory boards are a bit obstinate about clock relations
and may insert wait states when out of sync, even though the system
logic doesn't too much care on expansion bus cycles.

Some day, I may actually understand all of this...  1/2 8-)

-- 
George Robbins - now working for,	uucp: {uunet|pyramid|rutgers}!cbmvax!grr
but no way officially representing	arpa: cbmvax!grr@uunet.uu.net
Commodore, Engineering Department	fone: 215-431-9255 (only by moonlite)