Path: utzoo!attcan!uunet!husc6!ogccse!blake!uw-beaver!cornell!rochester!udel!burdvax!bbking!rmarks
From: rmarks@KSP.Unisys.COM (Richard Marks)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Different types of cache on 386's
Message-ID: <654@bbking.KSP.Unisys.COM>
Date: 23 Nov 88 16:23:17 GMT
References: <673@wa3wbu.UUCP>
Organization: Unisys/Knowledge Systems Organization, Frazer, PA
Lines: 30

In article <673@wa3wbu.UUCP> john@wa3wbu.UUCP (John Gayman) writes:
>      Can anyone tell me breifly what the difference is between "Direct
>Mapped Cache" and "Two-way Set Associative Cache" and why one would be
>preferred over the other ?  I usually see the first being a 32K and
>the second 64K.  Thanks.  This is on a 386 system.

I'll try. Basically all cache is addressed by the low bits of the address. 
The address in the cache is usually to the word (4 bytes) level.  So you
can always get something from the cache, the question is VALIDITY.

You get an extra 8 bits along with the 32 bits of data from the cache.
These 8 bits are compared with the next 8 bits of the address.  If they match,
you have cached data.  (The highest 8 bits must match or cache gets reset.
This is not a problem on a PC but it is on Unix).  So far I have described
"Direct Mapped Cache".

Now in most PC programs there is a seperate code and data segment.  Usually
these are addressed from the low segment offset; so low offsets are used
more frequently.  Thus considering the above DMC algorithm, there is a good
chance of having code and data access the same offset and thus the same
cache location.  This causes cache to keep reloading and reduces it's
effectiveness.  The two-way cache allows two segemnt addresses for the same
offset.  

I thought most 386 machines use DMC while the Motorola MMU'c use two-way.
Does anyone know which 386's use two way??  The 386 Unisys machines I know of
(the 6000/50 and PW850) use DMC.

Richard Marks
rmarks@KSP.unisys.COM