Xref: utzoo comp.arch:7246 comp.sys.misc:1952 Path: utzoo!attcan!uunet!mcvax!ukc!stc!stl!dww From: dww@stl.stc.co.uk (David Wright) Newsgroups: comp.arch,comp.sys.misc Subject: Re: 250 MHz SPARC implementation Message-ID: <864@acer.stl.stc.co.uk> Date: 15 Nov 88 21:51:22 GMT References: <19070@uflorida.cis.ufl.EDU> <414@aurora.auvax.uucp> <17839@glacier.STANFORD.EDU> Reply-To: dww@acer.UUCP (David Wright) Organization: STL,Harlow,UK. Lines: 34 In article <17839@glacier.STANFORD.EDU> jbn@glacier.UUCP (John B. Nagle) writes: # # Prism is making noises about building a 250MHz implementation of Sun's #SPARC architecture out of Gigabit Logic's gallium-arsenide MSI parts. This, #however, will not be a single chip, but a board. Interesting. What will they use for memory? Sun's implementation in the Sun 4 uses fast (block) access DRAM rather than cache memory, though I suppose there's no reason why cache cannot be used with the SPARC. But if the cache is on the virtual address side of the MMU (as it usually is with separate MMU's) it needs to be quite big. 4nSec GAs RAM I can believe, but BIG 4nSec GAs RAM? Another point - how big is this board? 4nSec * C is only a few inches. This is why single-chip RISC processors win out ultimately. CISC Mainframe processors which are many-chip get over the speed-of-light problem to some extent by pipelining instructions - eg 3 in 30nSec rather than one complete cycle in 10nSec. The SPARC architecture assumes only one instruction executed between a jump instruction and the intruction at the jump address. I guess you could 'unwind' extra ones from the pipeline but it wouldn't be simple. I'm not saying a 250Meg SPARC can't be done, just that it won't be easy. With the technology pushed that hard you get into vanishing returns, so it will be very expensive too. But if I'm wrong, and Prism make it both fast and (fairly) cheap, I WANT ONE! Disclaimer: I'm no expert on this: if you think you know better you're probably right. -- Regards, David Wright STL, London Road, Harlow, Essex CM17 9NA, UK dww@stl.stc.co.uk ...uunet!mcvax!ukc!stl!dww PSI%234237100122::DWW