Path: utzoo!attcan!uunet!husc6!think!ames!oliveb!sun!hanami!landman
From: landman%hanami@Sun.COM (Howard A. Landman)
Newsgroups: comp.sys.next
Subject: Re: PaRITY (was NeXT Memory - No Error Checking or Parity !)
Keywords: Memory,errors,parity
Message-ID: <78373@sun.uucp>
Date: 18 Nov 88 18:36:07 GMT
References: <549@gt-eedsp.UUCP> <7493@well.UUCP> <8794@spl1.UUCP>
Sender: news@sun.uucp
Reply-To: landman@sun.UUCP (Howard A. Landman)
Organization: Sun Microsystems, Mountain View
Lines: 18

In article <8794@spl1.UUCP> patterso@hardees.rutgers.edu (Ross Patterson) writes:
>Parity also allows your hardware to correct  the error,  and inform  you of it
>later.  You *CAN* have your cake  and eat  it too.   Systems  I've worked with
>before have had  SC/DD (Single-bit  Correct, Double-bit  Detect) hardware that
>informs the  error  logger  of exactly  which chip  on which  memory board got
>nailed.  The SC hardware lets you get your data out, and in  theory points out
>the problem before the chip deteriorates into causing a DD  (which doesn't get
>the data  out).    I  understand  that   IBM's  3090   series  has  Double-bit
>Correct/Triple-bit Detect logic.  Neato.

You're confusing parity with more complicated error detection/correction
schemes.  Parity is adding one bit, and gives you SED (single-error detection).
It does not allow for any correction, since you have no way of knowing which
bit is wrong (it might even be the parity bit).  SEC/DED requires a larger
overhead, and DEC/TED even more.
	Howard A. Landman
	landman@hanami.sun.com
	UUCP: sun!hanami!landman