Path: utzoo!attcan!uunet!ncrlnk!ncr-sd!hp-sdd!hplabs!nsc!stevew
From: stevew@nsc.nsc.com (Steve Wilson)
Newsgroups: comp.sys.nsc.32k
Subject: Re: AUTHOR SPEAKS: '532 Manifesto
Keywords: cheap nsc 532
Message-ID: <7880@nsc.nsc.com>
Date: 17 Nov 88 20:25:05 GMT
References: <433@sdrc.UUCP> <2659@sultra.UUCP>
Reply-To: stevew@nsc.nsc.com.UUCP (Steve Wilson)
Organization: National Semiconductor, Sunnyvale
Lines: 24

In article <2659@sultra.UUCP> dtynan@sultra.UUCP (Der Tynan) writes:
>Assuming something like a 20MHz '532, then the clock cycle is 50ns.  Hmm.  The
>memory cycle will probably be something close.  I'm not about to buy 4Mb of
>50ns SIMMS!.  Where's Steve Wilson when ya need him?  How about an *optional*
>64K cache?  Too much?  Oh well.

Huh, Whaa..Who Me! Some one call my name?.....Guess not, guess I'll
go back to sleep.  ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ

Seriously,  you should be able to put an external cache on the 532 at 20Mhz
with no great shakes.  Just going though the numbers in my head I'd guess
you would have to use 50ns static SRAMS for the cache at 20Mhz. I'd 
think it might be easier to build a Page mode or Static Column based
DRAM system that supported burst. This might be a useful alternative
to a cache AND drams.  A local gentleman named George Scolaro was 
yelling to me yesterday about such a fantasy.  (Oh my, another George! ;-)
Hey Mr. Scolaro, do you read this net?

Steve Wilson
32K Architecture Group
National Semiconductor, Santa Clara