Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ucbvax!hplabs!hpda!hpcuhb!hpcllla!daryl From: daryl@hpcllla.HP.COM (Daryl Odnert) Newsgroups: comp.arch Subject: HP Precision Architecture Info Message-ID: <960009@hpcllla.HP.COM> Date: 13 Dec 88 22:01:02 GMT Organization: HP CSG/DLD California Language Lab Lines: 137 comp.arch fans know that it is fairly common to see information/ arguments about SPARC, MIPS, 88K, 68K, and others in this group. For a variety of reasons, the HP Precision architecture is not discussed much here in comp.arch. (Although I would like to thank John Mashey of MIPS, who always seems to remember to mention HP whenever he talks who is serious about RISC machines.) For reasons which I won't go into here, HP discourages us engineers from posting information such as benchmark timings and future product specifications to publicly readable news groups. If, however, you are interested in reading about the HP Precision architecture, I've listed a bibliography below of HP authored articles and manuals related to the HPPA. (This is a first draft of the bibliography, so I apologize to anyone who wrote something that I neglected to include.) I hope to expand it to include other materials including non-HP authored articles and books, so if you know of any such references, please send me the info. Briefly, the HP Precision Architecture is a non-window-RISC-like architecture. o 32 general purpose 32-bit registers in the CPU. o 64-bits of virtual addressing space. o Only loads-stores access memory o Pipelined CPU o Delayed branches o Lots of interesting little features in the instruction set (just to make it fun for us compiler writers to work on :-) o Floating-point coprocessor is IEEE standard, has 12 registers (which can be used for single or double precision values) plus 4 status/exception registers o Runs HP-UX (our version of UN*X) o Runs MPE/XL (our commercial transaction processing operating system, which means, believe it or not, we know how to compile COBOL and RPG onto a RISC.) I would recommend reading both the Birnbaum and the Mahon HP Journal articles for general introductions to HPPA. Enjoy, Daryl Odnert daryl%hpcllla@hplabs.hp.com Hewlett-Packard California Language Lab 19447 Pruneridge Ave. MS 47LH Cupertino, CA 95014 Permission to copy this bibliography is granted. ---------- HP Precision Architecture Bibliography Last updated 12/88 Please mail any additions/corrections to: Daryl Odnert daryl%hpcllla@hplabs.hp.com Hewlett-Packard California Language Lab 19447 Pruneridge Ave. MS 47LH Cupertino, CA 95014 J. S. Birnbaum and W. S. Worley, Jr., "Beyond RISC: High-Precision Architecture," Hewlett-Packard Journal, Vol. 36, No. 8, August 1985. D. S. Coutant, C. L. Hammond, and J. W. Kelly, "Compilers for the New Generation of Hewlett-Packard Computers," Hewlett-Packard Journal, Vol. 37, No. 1, January 1986. HP Precision Architecture Procedure Calling Conventions Reference Manual, Hewlett-Packard Company, 1986. HP part number 09740-90015. HP Precision Architecture and Instruction Reference Manual, Hewlett-Packard Company, 1986. HP part number 09740-90014. Mark S. Johnson and Terrence C. Miller, "Effectiveness of a Machine-Level, Global Optimizer," Proc. of the SIGPLAN '86 Symp. on Compiler Construction, ACM SIGPLAN Notices, Vol. 20, No. 7, July 1986. D. S. Coutant, "Retargetable High-Level Alias Analysis", Conference Record of the 13th ACM Symposium on Principles of Programming Languages, January 1986. P. Gibbons and S. Muchnick, "Efficient Instruction Scheduling for a Pipelined Architecture," Proceedings of the SIGPLAN '86 Symposium on Compiler Construction, ACM SIGPLAN Notices, Vol. 20, No. 7, July 1986. M. J. Mahon, et. al., "Hewlett-Packard Precision Architecture: The Processor," Hewlett-Packard Journal, Vol. 37, No. 8, August 1986. D. V. James, et. al., "Hewlett-Packard Precision Architecture: The Input/Output System," Hewlett-Packard Journal, Vol. 37, No. 8, August 1986. Alan S. Brown, et. al., "Data Base Management for HP Precision Architecture Computers," Hewlett-Packard Journal, Vol. 37, No. 12, December 1986. F. W. Clegg, et. al., "The HP-UX Operating System on HP Precision Architecture Computers," Hewlett-Packard Journal, Vol. 37, No. 12, December 1986. K. W. Pettis and W. B. Buzbee, "Hewlett-Packard Precision Architecture Compiler Performance," Hewlett-Packard Journal, Vol. 38, No. 3, March 1987. David A Fotland, et. al., "Hardware Design of the First HP Precision Architecture Computers," Hewlett-Packard Journal, Vol. 38, No. 3, March 1987. D. J. Magenheimer, L. Peters, K. Pettis, and D. Zuras, "Integer Multiplication and Division on the HP Precision Architecture," Proc. of the Second Intl. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-II), ACM, New York, October 1987. Steven T. Mangelsdorf, et. al., "A VLSI Processor for HP Precision Architecture," Hewlett-Packard Journal, Vol. 38, No. 9, Sept. 1988. J. Busch, et. al., "MPE/XL: The Operating System for HP's Next Generation of Commercial Computer Systems," Hewlett Packard Journal, Vol. 38, No. 11, December 1987. Jeffry D. Yetter, et. al., "HP Precision Architecture NMOS-III Single Chip CPU," Hewlett-Packard Journal, Vol. 38, No. 9, Sept. 1988. Craig S. Robinson, et. al., "A Midrange VLSI Hewlett-Packard Precision Architecture Computer," Hewlett-Packard Journal, Vol. 38, No. 9, Sept. 1988. Gerald R. Gassman, et. al., "VLSI-Based High-Performance HP Precision Architecture Computers," Hewlett-Packard Journal, Vol. 38, No. 9, Sept. 1988. D. Coutant, S. Meloy, and M. Ruscetta, "DOC: A Practical Approach to Source-Level Debugging of Globally Optimized Code", Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation, June 1988. S. Jain and C. Thompson, "An Efficient Approach for Data Flow Analysis in a Multiple Pass Global Optimizer", Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation," June 1988.