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From: lethin@athena.mit.edu (Richard A Lethin)
Newsgroups: comp.arch
Subject: Testability Features
Message-ID: <8453@bloom-beacon.MIT.EDU>
Date: 14 Dec 88 23:47:03 GMT
Sender: daemon@bloom-beacon.MIT.EDU
Reply-To: lethin@wheaties.ai.mit.edu (Richard A Lethin)
Organization: Massachusetts Institute of Technology
Lines: 30


I'm curious about how people designing RISC chips and microprocessors
test them.  We're designing a small VLSI processor here and would like
to do it right.

There seem to be lots of great algorithms for strictly combinational
circuits, but when state gets added, the answer seems to be "make
every register shiftable" to allow the circuit to be analyzed 
as a combinational circuit.

A RISC chip, with a bunch of on-chip registers, a TLB, pipeline
registers, a limited number of IO pins, and irregular logic would seem
to be a testability nightmare.  But gunking up a pipeline register to
make it shiftable seems drastic.  The state's not regular enough, like
a DRAM, to just run patterns, so, how is it done?

How about testing the small, on-chip data cache?  That certainly
isn't going to be made shiftable...

What specific testability features are added to the chip? LSSD?
OCMS? Special opcodes?  RESET? Special test pins or pads?

Are test vectors generated by hand?  If so, how long does that take?
And who does it?  If not, how are they generated?

How much coverage do you get?  Is the coverage satisfactory?

How long does it take to run the vectors on the chip?  What hardware
do you use?

-- Rich