Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!oliveb!pyramid!prls!mips!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Re: Testability Features
Message-ID: <9997@obiwan.mips.COM>
Date: 15 Dec 88 17:18:37 GMT
References: <8453@bloom-beacon.MIT.EDU>
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 21

In article <8453@bloom-beacon.MIT.EDU>,
    lethin@wheaties.ai.mit.edu (Richard A Lethin) writes:
$ A RISC chip, with a bunch of on-chip registers, a TLB, pipeline
$ registers, a limited number of IO pins, and irregular logic would seem
$ to be a testability nightmare.  But gunking up a pipeline register to
$ make it shiftable seems drastic.  The state's not regular enough, like
$ a DRAM, to just run patterns, so, how is it done?
$ 
$ What specific testability features are added to the chip? LSSD?
$ OCMS? Special opcodes?  RESET? Special test pins or pads?

Several of the RISC chips under construction in bipolar ECL technology
are using LSSD-like scan paths.

And people have this belief, founded or unfounded, that however difficult
it is to test a RISC chip, it's *more* difficult to test a CISC chip
having an equal number of circuits.  You know, simplicity breeds
observability. :-)
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
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