Path: utzoo!attcan!uunet!ncrlnk!ncrcae!hubcap!gatech!ncar!tank!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Testability Features
Message-ID: <28200252@mcdurb>
Date: 16 Dec 88 19:09:00 GMT
References: <8453@bloom-beacon.MIT.EDU>
Lines: 14
Nf-ID: #R:bloom-beacon.MIT.EDU:8453:mcdurb:28200252:000:675
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Dec 16 13:09:00 1988


..> Richard A. Lethin of MIT asks about testing of VLSI RISCs
..> and Mark Johnson of MIPs makes some comments.

Talking about testing, I finally think that I have figured out
one of the things that has been bothering me about hardware
testability methodology.
    Most VLSI test methodology seems oriented towards detecting
*implementation* or *fabrication* errors, not *design* errors.
Ie. the tests look for bad transistors, or mis-wirings; they
don't look for adherence to higher level specs.
    When people talk about test coverage, they mean test coverage
over a limited space of implementation and fabrication errors,
not over the much larger space of design errors.