Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cwjcc!hal!nic.MR.NET!eta!pwcs!ems!srcsip!shankar
From: shankar@src.honeywell.COM (Son of Knuth)
Newsgroups: comp.arch
Subject: Re: Content Addressible Memories
Message-ID: <13582@srcsip.UUCP>
Date: 16 Dec 88 17:45:31 GMT
References: <00051@meph.UUCP> <6746@june.cs.washington.edu>
Reply-To: shankar@wabasha.UUCP (Subash Shankar)
Organization: Honeywell Systems & Research Center, Camden, MN
Lines: 14

In article <6746@june.cs.washington.edu> rik@june.cs.washington.edu (Rik Littlefield) writes:
> [problems with using a fixed width CAM to access words when the number
>  of bits in the index is larger then the CAM width]
>
>--Rik

It is not difficult to design CAMs with chaining capability.  Probably the
simplest way to include this capability is to store a multi-word record
in contiguous words, and allow the capability to shift the mark bits 
(or response registers as some prefer to call it) one bit down.  To match
a multi-word record, you just match one word, then shift the mark bits
one place, match the next word, and on and on.  

Does the AMD product described previously have chaining capability?