Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!njin!princeton!siemens!demon!fwb
From: fwb@demon.siemens.com (Frederic W. Brehm)
Newsgroups: comp.arch
Subject: Re: Testability Features
Message-ID: <4916@siemens.UUCP>
Date: 19 Dec 88 18:26:38 GMT
References: <8453@bloom-beacon.MIT.EDU> <28200252@mcdurb>
Sender: news@siemens.UUCP
Reply-To: fwb@demon.UUCP (Frederic W. Brehm)
Organization: Siemens Research and Technology Laboratories
Lines: 25

In article <28200252@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:
>Talking about testing, I finally think that I have figured out
>one of the things that has been bothering me about hardware
>testability methodology.
>...
>    When people talk about test coverage, they mean test coverage
>over a limited space of implementation and fabrication errors,
>not over the much larger space of design errors.

Hmmmm.  Are you suggesting that each and every part out of the fab be
tested for DESIGN errors?  I hope not.  Tests for design errors should be
done before the design is committed to high volume production.

Design tests are usually done by running simulation software (e.g. Spice)
and testing the first samples off the production line in high-end testers
and prototype circuits.

Fred
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