Path: utzoo!attcan!uunet!husc6!rutgers!att!whuts!homxb!houxv!wad
From: wad@houxv.UUCP (R.WADSACK)
Newsgroups: comp.arch
Subject: Re: Testability Features
Summary: see IEEE Design & Test of Computers article
Message-ID: <826@houxv.UUCP>
Date: 19 Dec 88 16:21:48 GMT
References: <8453@bloom-beacon.MIT.EDU> <28200252@mcdurb> <8496@bloom-beacon.MIT.EDU>
Organization: AT&T Bell Labs, Holmdel, NJ
Lines: 28

> you've got at least three sets of tests to develop:
> 
>  "Manufacturing Tests"
>  "Validation Tests"
>  "Diagnostic Tests"
> 
> with different time and coverage constraints.
> 
> And how do people go about finding design errors anyway?
> 
> Would any real-life diagnostic engineers care to comment?
> 
 
I wrote up my experiences with the AT&T WE 32100 CPU's in an
article in the August 1984 issue of "IEEE Design and Test of Computers"
(pp. 66 - 75).
 
It's titled "Design Verification and Testing of the WE 32100 CPUs".
It treates the differences between DV tests, silicon tests, and
diagnostic tests.
 
I have also done equivalent work on the Bell Labs Crisp "RISC"
CPU.  The concepts and approaches are much the same regardless
of whether the chip at hand is CISC or RISC.
 
		Ronald L. Wadsack
		AT&T Bell Labs
		Holmdel, NJ