Path: utzoo!attcan!uunet!husc6!rutgers!rochester!pt.cs.cmu.edu!k.gp.cs.cmu.edu!lindsay
From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: GaA
Keywords: on chip cache
Message-ID: <3922@pt.cs.cmu.edu>
Date: 22 Dec 88 03:07:20 GMT
References: <3417@uoregon.uoregon.edu>
Organization: Carnegie-Mellon University, CS/RI
Lines: 16

In article <3417@uoregon.uoregon.edu> tmandadi@uoregon.uoregon.edu (tilak mandadi) writes:
> Can somebody explain me why we can't have on chip cache in RISCs using
> GaA technology ? thanks.

If you mean gallium arsenide (GaAs), then the answer is that it isn't
available yet.

This is a very exciting year for GaAs fans. Several players have just
announced gate arrays at the 10,000 gate level. That's enormous by the
standards of a year or two ago.  Getting the technology into production
just took a lot more struggle than some of us predicted.

In time, someone (or lots of people) will build the chip you asked for.
There's no reason why 500 MHz isn't achievable. But you'll have to wait.
-- 
Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science
--