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From: mccalpin@loligo.fsu.edu (John McCalpin)
Newsgroups: comp.arch,comp.lang.fortran,comp.misc
Subject: Re: Quadruple-Precision Floating Point ?
Keywords: REAL*16 hardware
Message-ID: <285@loligo.fsu.edu>
Date: 20 Dec 88 13:27:35 GMT
References: <8561@alice.UUCP> <3688@s.cc.purdue.edu>
Reply-To: mccalpin@masig1.ocean.fsu.edu (John D. McCalpin)
Organization: Supercomputer Computations Research Institute
Lines: 25

In article <3688@s.cc.purdue.edu> ags@s.cc.purdue.edu (Dave Seaman) writes:
>In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes:
>>Are there any machines that implement quad-precision (128-bit) floating
>>point numbers in hardware?
>Basically all of the CDC, ETA, and Cray machines support 128-bit floating
>point numbers, but it is called double precision, not quad precision.
>Dave Seaman	ags@j.cc.purdue.edu

Although it is true that CDC/ETA and Cray machines have the ability to 
do 128-bit arithmetic, you probably don't want to do it on these machines.
The relative speed of 64-bit vector instructions vs 128-bit instructions
(which cannot currently be vectorized) is typically very close to 100:1
on both the CDC/ETA and Cray machines.  Of course, if your code is all
scalar anyway, then the performance degradation will not be so severe.

It is theoretically possible to re-write the microcode in the Cyber 205
vector pipes to perform 128-bit vector instructions, but CDC has decided
that there is not much of a market for it.  This same approach cannot be
used on the ETA-10, since the instructions are all in hardware -- which
makes debugging the "microcode" a rather painful experience.

John D. McCalpin
mccalpin@masig1.ocean.fsu.edu
mccalpin@nu.cs.fsu.edu
mccalpin@fsu	(BITNET or MFENET)