Path: utzoo!attcan!uunet!cbmvax!daveh From: daveh@cbmvax.UUCP (Dave Haynie) Newsgroups: comp.sys.cbm Subject: Re: C-128 MMU techniques and memory maps Message-ID: <5504@cbmvax.UUCP> Date: 14 Dec 88 18:54:44 GMT References: <2140@nunki.usc.edu> Organization: Commodore Technology, West Chester, PA Lines: 89 in article <2140@nunki.usc.edu>, aliu@nunki.usc.edu (Alejandro Liu) says: > Keywords: C-128, MMU, virtual memory, memory map > Hi UseNet Users: > I have been reading some of the specs about the C-128, because a > program I am writing, and I need some information. Sounds to me like you need a C128 Programmer's Reference Manual. > First I heard that the 128's MMU can handle 1 Meg of memory, Nope. The current MMU is limited to 128K of RAM, plus the ROM. In theory, the MMU design would permit an MMU to be built that would support 1 meg of RAM, though in practice, only 256K of RAM would be possible without some software problems (the banking method _changes_ when you go over 256k). > Second, How do you use the MMU to do Bank Switching? I know there is a > register at location $FF00, but what does each bit means? The MMU register map looks something like this: Location Register $D500 Configuration Register $D501 Preconfiguration Register A $D502 Preconfiguration Register B $D503 Preconfiguration Register C $D504 Preconfiguration Register D $D505 Mode Configuration Register $D506 RAM Configuration Register $D507 Page 0 Pointer LOW $D508 Page 0 Pointer HIGH $D509 Page 1 Pointer LOW $D50A Page 1 Pointer HIGH $D50B MMU Version Register $FF00 Configuration Register (same as $D500) $FF01 Load Configuration Register A $FF02 Load Configuration Register B $FF03 Load Configuration Register C $FF04 Load Configuration Register D The configuration and preconfiguration registers have the same format: Bit 7: Unused (for 256K banking in a new MMU) Bit 6: Select RAM bank 0 or 1 Bit 5,4: ROM HI Space (00 = System ROM, 11 = RAM) Bit 3,2 ROM MID Space (00 = System ROM, 11 = RAM) Bit 1: ROM LOW Space ( 0 = System ROM, 1 = RAM) Bit 0: I/O Space (0 = System I/O, 1 = HIGH ROM Space) If you write to the CR, the banking takes place immediately. If you write to a PCR, nothing immediately happens. If you write to an LCR (doesn't matter what you write), the contents of the corresponding PCR get transferred to the CR and the banking gets set. This allows several common setups to be stored and used without having to have I/O space turned on or having to disturb a register. The RAM Configuration register looks like this: Bit 7: Unused (for 256K banking in a new MMU) Bit 6: Select bank 0 or 1 for the VIC chip Bit 5,4: For expansion banking beyond 256K in a new MMU Bit 3: Sharing banks at top of RAM (0 = Not Shared, 1 = Shared) Bit 2: Sharing banks at bottom of RAM (0 = Not Shared, 1 = Shared) Bit 1,0: Amount shared (00 = 1K, 01 = 4K, 10 = 8K, 11 = 16K) The page registers specify the actual location of the 8502's page 0 and 1. Bit 0 of each HIGH register specifys the bank, while the LOW register specifys the page in that bank. You should write first to the high register, then to the low, for each pair. > I know that there is a Kernal subroutine that calculates the > value, but I don't like the 15 Bank system they have a Commodore. > What are the exact additions to the Kernal Jump table? I only know > the old jumping points, but I know that they have added quite a few > subroutines, I would like to know what are them and where are they. I don't know how the software works, maybe Fred will say something about it. You should really get the C128 Programmer's Reference Manual, which tell all about this stuff. And I'm not just saying that 'cause I helped write it :-) > aliu@nunki.usc.edu (Alejandro Liu) > (Simple .signature, $CHEAP$) -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy Amiga -- It's not just a job, it's an obsession