Path: utzoo!attcan!uunet!xpiinc!tmt
From: tmt@xpiinc.UU.NET (Thomas M. Talpey)
Newsgroups: comp.sys.m68k
Subject: Re: addq.w #n,sp and a pop quiz
Keywords: C asm addq
Message-ID: <196@xpiinc.UU.NET>
Date: 13 Dec 88 18:21:59 GMT
References: <5005@bsu-cs.UUCP> <5460@cbmvax.UUCP> <1100@ncar.ucar.edu> <1737@oakhill.UUCP> <2805@uhccux.uhcc.hawaii.edu>
Reply-To: tmt@xpiinc.UUCP (Thomas M. Talpey)
Distribution: na
Organization: Visual Technology Incorporated / Xpi Division, Providence, R.I.
Lines: 39


>> Dave Trissel asks...
>> There is only one place in the instruction set where a data register is
>> implicitly sign-extended. Where?

Movemw to data regs. Is this because of microcode streamlining so the
processor doesn't have to figure out whether it's an address or data
reg regarding extension? The practical reasons seem marginal. Also, why
does movem overshoot by one memory cycle? Inquiring minds want to know.

>> Mike Morton asks:

Hey, you're cheating (I think!).

>>   - what's the fastest way to bump two address regs each by one byte?

	cmpmb	ax@+,ay@+	| 12 cycles

But it adds one memory cycle over two addql's (16 cycles). This may or may
not make it faster.

>>   - what's faster than an SCS instruction, but equivalent (except
>>     for CCR, perhaps)

	subxb	dx,dx		| 4 cycles

But it assumes that the X bit is set with CY, only sometimes true!

>>   - can you do Max(Dx,Dy) or Min in four instructions?

	movl	Dx,result
	cmpl	Dx,Dy
	bles	.+4
	movl	Dy,result

Have you got a better way?

Tom Talpey
tmt@xpiinc.uu.net