Path: utzoo!utgpu!attcan!uunet!lll-winken!lll-tis!ames!xanth!nic.MR.NET!tank!uxc!uxc.cso.uiuc.edu!m.cs.uiuc.edu!grabas
From: grabas@m.cs.uiuc.edu
Newsgroups: comp.sys.next
Subject: Re: transputers
Message-ID: <61300002@m.cs.uiuc.edu>
Date: 15 Dec 88 21:11:00 GMT
References: <8304@pasteur.Berkeley.EDU>
Lines: 33
Nf-ID: #R:pasteur.Berkeley.EDU:8304:m.cs.uiuc.edu:61300002:000:1578
Nf-From: m.cs.uiuc.edu!grabas    Dec 15 15:11:00 1988



	Talking of transputers in a few words is hard, and I have very little 
time (Finals' week...). To have more information, you could read the 
Transputer notesfile. I don't know how it si called at berkeley; here (U of I) 
this notesfile is called comp.sys.next and the transputer one is called 
comp.sys.transputer. 

	A transputer is an integrated circuit comprising: 
	-A 32-bit RISC-like CPU
	-A 64-bits FPU (IEEE standard) 
	-A certain amount of on-chip memory (4K currently) 
	-A certain number of communication links for inter-transputers 
	 communication. Each link implements two DMA channels (one read, one 
	 write) between memory and a bit-serial line. the links work at up to 
	 20Mbits/ second; there are 4 of them on the current implementation 
	 (T800) 
	-A memory controller which allows the connection of a transputer do 
	 dynamic RAM without any additionnal logic (the controller takes care 
	 of the refresh cycles, etc...) 

	To sum-up, you can built a parallel machine using transputers 
connected one to the other with their links; you do not need any memory with 
your transputers because they have on-chip memory and can be booted from a 
link instead of from ROM. Anyway, if you want to boot them from ROM, or 
increase their memory using external memory chip, you do not need any 
extra logic (well, may be an address latch, because addresses and data are 
multiplexed on certain models) to run the system. 

		This may not be 100% clear and detailed, but I do not have a 
lot of time today... 

		Dominique Grabas, University of Illinois at U-C.