Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!ukma!rutgers!cmcl2!husc6!rice!sun-spots-request
From: MKL@sri-nic.arpa (Mark Lottor)
Newsgroups: comp.sys.sun
Subject: 3/50 memory chip map
Message-ID: <12453885457.28.MKL@SRI-NIC.ARPA>
Date: 20 Dec 88 08:27:15 GMT
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Organization: Sun-Spots
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Approved: Sun-Spots@rice.edu
Original-Date: Mon, 12 Dec 88 11:16:02 PST
X-Sun-Spots-Digest: Volume 7, Issue 64, message 1 of 12

I decoded the 3/50 memory chip layout a while back.  The following is from
my notes.  If you run memory diagnostics, when you get a failure it will
give you the physical address of the error, and the XOR'd value of what
was written with what was read back.  The address tells you which bank of
chips, and the XOR tells you what bit (and thus the exact chip to
replace).  If the XOR was 0, then it's one of the four parity bits (p0-3)
and I don't know how to tell which one (you'd have to replace 4 chips).
Assuming you label the address bits as An-A0, with A0 as the least
significant bit, then bits A10,A2 tell you which bank.  I labeled the data
bits as 31-0 (0 least significant).

A10 | A2  |
===================
  0 |  0  |  bank 0
  0 |  1  |  bank 1
  1 |  0  |  bank 2
  1 |  1  |  bank 3


The PC board layout is like this:

x <==Corner of PC Board here

             Bank
  |  3  |  2  |  1  |  0  |

   X  W  V  U  T  S  R  P   <==PC Board markings
==========================
48|     |     |     |p3 p1
47|     |     |     |31 15
46|                  30 14
45|                  29 13
44|                  28 12  <== the memory chips
43|                  27 11
42|                  26 10
41|                  25  9
40|                  24  8
39|                  p2 p0
38|                  23  7
37|                  22  6
36|                  21  5
35|                  20  4
34|                  19  3
33|                  18  2
32|                  17  1
31|                  16  0
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