Path: utzoo!attcan!uunet!husc6!rutgers!rochester!pt.cs.cmu.edu!andrew.cmu.edu!jk3k+
From: jk3k+@andrew.cmu.edu (Joe Keane)
Newsgroups: comp.arch
Subject: Re: SPARC vs. MIPS on gcc
Message-ID: <4XgSiay00XcQADi0Vf@andrew.cmu.edu>
Date: 23 Dec 88 06:45:58 GMT
References: <82150@sun.uucp> <697@hscfvax.harvard.edu>,
	<3779@druhi.ATT.COM>
Organization: Carnegie Mellon
Lines: 8
In-Reply-To: <3779@druhi.ATT.COM>

I call a win for MIPS.  MIPS has 15% more instructions, accounted for almost
exactly by the difference in NOPs (everything else balances out).  SPARC has 34%
more raw cycles, due mostly to (surprise, surprise) loads and stores.
Unfortunately, the M1000 seems to lose big from a too-small cache.  But i have
no doubt that (at any given time) the newest MIPS implementation should have
more MHz and a bigger cache than the newest SPARC implementation.  Flame away...

--Joe