Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cwjcc!gatech!ncar!ames!oliveb!sun!hanami!landman
From: landman%hanami@Sun.COM (Howard A. Landman)
Newsgroups: comp.arch
Subject: Re: GaA
Keywords: on chip cache
Message-ID: <83086@sun.uucp>
Date: 27 Dec 88 20:13:29 GMT
References: <3417@uoregon.uoregon.edu>
Sender: news@sun.uucp
Reply-To: landman@sun.UUCP (Howard A. Landman)
Organization: Sun Microsystems, Mountain View
Lines: 11

In article <3417@uoregon.uoregon.edu> tmandadi@uoregon.uoregon.edu (tilak mandadi) writes:
> Can somebody explain me why we can't have on chip cache in RISCs using
> GaA technology ? thanks.

Yield decays exponentially with chip area (at the upper limit).  Current
GaAs fabrication doesn't allow economical production of chips that complex.

Give it a few more years.

	Howard A. Landman
	landman@hanami.sun.com