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From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Info on intel microarchitectures
Message-ID: <12977@cup.portal.com>
Date: 27 Dec 88 06:17:52 GMT
Organization: The Portal System (TM)
Lines: 35

> request for sources on details of Intel 86/286 microarchitectures

The most detailed writeup I've seen on the 8086 and 80286 internal design
is Intel's patents on the chips.  They're not exactly tutorial, and may not
match the commercial implementation in every respect, but there is a lot
of information there.

Patent 4,363,091 covers a variety of aspects of the 8086, including the
segmented addressing scheme, byte/word data adjustments, and automatic
sign extension of variable-length data.  (The claims are, of course, much
more specific than these brief summaries.)  The coprocessor interface and
string instructions are also covered.

Patent 4,449,184 is a division of the same application as the patent
described above, and covers the division of the processor into the
bus interface unit and the execution unit, with the pre-fetch queue
between them.

Perhaps the most interesting is patent 4,442,484, which covers the 
memory management scheme of the 286.  This patent is the one that is
likely to cause big trouble for anyone attempting to clone the 286 or
386 architecture.  In fact, it appears that it may affect not just a
clone, but anything that is binary-compatible.

You can get copies of patents for $1.50 each from the U.S. patent office
is Washington, DC; it supposedly takes 1-2 months.  I ordered a patent
from them in July and have yet to receive it.  If you live near
Sunnyvale, CA, they have a very nice patent library.  Our company
provides several bound patent collections, including IBM RISC patents,
IBM PC/AT patents, and the Intel patents listed above.  The set of three
Intel patents costs $20 postpaid ($25 outside US and Canada; add tax in
California).

Michael Slater, Microprocessor Report   mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306  415/494-2677