Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!gatech!purdue!decwrl!decvax!tektronix!percival!qiclab!neighorn
From: neighorn@qiclab.UUCP (Steve Neighorn)
Newsgroups: comp.arch
Subject: Re: Architecture Books and the Whereabouts of Glenford Myers
Message-ID: <1926@qiclab.UUCP>
Date: 31 Dec 88 18:07:00 GMT
References: <5881@saturn.ucsc.edu>
Reply-To: neighorn@qiclab.UUCP (Steve Neighorn)
Organization: Qic Laboratories, Portland, Oregon.
Lines: 26

In article <5881@saturn.ucsc.edu> haynes@saturn.ucsc.edu (Jim Haynes - Computer Center) writes:
>While we're at it, what is the 80960, anyway?

I would be glad to fill you in on a few 80960 details:

The 80960 is a 32-bit CPU from Intel. The 80960KA (base architecture) includes
16 32-bit global registers, and 4 sets of 16 32-bit local registers that are
made available for a routine invoked with "call." These local register sets are
cached on-chip. Additional sets are flushed to memory. The KA also has a
256 programmable vector interrupt controller, a 512-byte instruction cache,
a 32-bit multiplexed burst bus (burst can load 4 words at a time), register
scoreboarding, and a rich instruction set.

The 80960KB adds an IEEE-754 compliant FPU, with single, double, and extended
(80-bit) precision operations. It has four 80-bit floating point registers, and
is clocked at around 4 megawhetstones.

The 80960MC adds memory management capabilities.

I know this is a quickie description, and I (or others) would be glad to
answer more specific questions if you have them.
-- 
Steven C. Neighorn            !tektronix!{psu-cs,reed,ogccse}!qiclab!neighorn
Intel Corporation            "Where we BUILD the Star Fighters that defend the
Development Tools Operation      frontier against Xur and the Ko-dan Armada"
80960 Language Group            work: (503) 696-7264 / home: (503) 645-7015