Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!bu-cs!purdue!decwrl!sun!pitstop!sundc!seismo!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: 64 bits
Message-ID: <13096@cup.portal.com>
Date: 31 Dec 88 19:54:51 GMT
References: <28200249@mcdurb> <451@babbage.acc.virginia.edu> <1951@scolex> <1723@elxsi.UUCP>
Organization: The Portal System (TM)
Lines: 16

>The (ELXSI) instruction set is not risc, but is
>much closer to a risc than to a VAX -- typical cpi for our latest CPU (which
>is made out of 2 big boards of ECL) is significantly less than 2.

Hmmm, this is interesting.  I claim CPI has very little to do with the
RISCiness or CISCiness of a *architecture*, to which the classifications
refer.  The reasons are:  (1) CPI is heavily determined by implementation,
but implementations are not CISC or RISC (perhaps they ought to be, or we
should have classifications for implementations) and (2) CPI is heavily
determined by what instructions are executed, e.g., I can write a program
that uses only the fast instructions of the upcoming re-implementations
of popular CISCs to get the CPI down (this is, in fact, what the updated
compilers for these micros will do), but does this make these architectures
RISCs?  Perhaps some would argue yes, but realistically, the architecture
hasn't changed, i.e., the old, slow instruction are still there, and they
are still slow (and old :-).  Comments?