Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cwjcc!gatech!gitpyr!loligo!mccalpin
From: mccalpin@loligo.fsu.edu (John McCalpin)
Newsgroups: comp.arch
Subject: Re: MIPS supports 80- & 128-bit floats.
Summary: What is 128-bit format?
Keywords: multiple-precision floating-point, IEEE standard floating-point
Message-ID: <325@loligo.fsu.edu>
Date: 1 Jan 89 16:12:36 GMT
References: <10452@obiwan.mips.COM>
Reply-To: mccalpin@masig1.ocean.fsu.edu (John D. McCalpin)
Organization: Supercomputer Computations Research Institute
Lines: 26

In article <10452@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>
>The MIPS instruction set includes opcodes for manipulating IEEE-standard
>80-bit and 128-bit floating point numbers.  As I recall, the IEEE
>standard calls them double-extended (80b) and quad (128b).
>
> -- Mark Johnson	
> 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086

What format is used for the IEEE 128-bit numbers?  All I have read 
is the original proposed draft standard, and I don't recall this
length.  Specifically, what size exponent does the 128-bit format use?

There is some hesitancy in the supercomputer community to switch to the
IEEE format because the exponent range of 64-bit numbers is so much
smaller than the range currently provided by Cray and CDC/ETA formats.
The IEEE 64-bit allows a range of about 1.0e-308 to 1.0e+308, while the
Cray and CDC/ETA machines allow a range of about 1.0e-4000 to 1.0e+4000.

I do not believe that the 80-bit format increases the exponent range.
It might help if the 128-bit format did allow this.....

John D. McCalpin
mccalpin@masig1.ocean.fsu.edu
mccalpin@nu.cs.fsu.edu
mccalpin@fsu	(BITNET or MFENET)