Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!purdue!decwrl!nsc!taux01!cjosta
From: cjosta@taux01.UUCP (Jonathan Sweedler)
Newsgroups: comp.arch
Subject: Re: MIPS supports 80- & 128-bit floats.
Keywords: multiple-precision floating-point, IEEE standard floating-point
Message-ID: <966@taux01.UUCP>
Date: 2 Jan 89 07:12:17 GMT
References: <10452@obiwan.mips.COM> <325@loligo.fsu.edu>
Reply-To: cjosta@taux01.UUCP (Jonathan Sweedler)
Organization: National Semiconductor (Israel) Ltd.
Lines: 44

In article <325@loligo.fsu.edu> mccalpin@masig1.ocean.fsu.edu (John D. McCalpin) writes:
>In article <10452@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>>
>>The MIPS instruction set includes opcodes for manipulating IEEE-standard
>>80-bit and 128-bit floating point numbers.  As I recall, the IEEE
>>standard calls them double-extended (80b) and quad (128b).
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                                     see below
>
>What format is used for the IEEE 128-bit numbers?  All I have read 
>is the original proposed draft standard, and I don't recall this
>length.  Specifically, what size exponent does the 128-bit format use?
>
>There is some hesitancy in the supercomputer community to switch to the
>IEEE format because the exponent range of 64-bit numbers is so much
>smaller than the range currently provided by Cray and CDC/ETA formats.
>The IEEE 64-bit allows a range of about 1.0e-308 to 1.0e+308, while the
>Cray and CDC/ETA machines allow a range of about 1.0e-4000 to 1.0e+4000.
                                                  ^^^^^^^^^^^^^^^^^^^^^^
                                                       see below

The IEEE Standard 754 defines Single Extended precision and Double
Extended precision numbers (I'm not sure about 854 but I *guess* it's
the same).  A single extended precision number is defined to have
more than 42 bits with an exponent field greater than 10 bits and a
fraction field greater than 30 bits.  A double extended precision
number is defined to have more than 78 bits with an exponent field
greater than 14 bits and a fraction field greater than 62 bits.
Note that the EXACT size of these precisions is not given. 

With this definition, double extended precision numbers have an exponent
range of AT LEAST 1.0e-4931 to 1.0e+4931.

The Intel 80x87 line and Motorola 68881 line use a 15 bit exponent
field (the minimum required for double extended precision) and a 
64 bit fraction field internally (of course these particular widths are 
not REQUIRED by the IEEE standard).  

So not only does the IEEE standard allow formats that give the range of
current supercomputers, but some implementations even support it! :-).
-- 
Jonathan Sweedler  ===  National Semiconductor Israel
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