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From: pcg@aber-cs.UUCP (Piercarlo Grandi)
Newsgroups: comp.arch
Subject: Re: 64 bits
Summary: RISC also means that complex instructions slow down simple ones
Message-ID: <476@aber-cs.UUCP>
Date: 3 Jan 89 00:38:36 GMT
Reply-To: pcg@cs.aber.ac.uk (Piercarlo Grandi)
Distribution: eunet,world
Organization: Dept of CS, UCW Aberystwyth, Wales
	(Disclaimer: my statements are purely personal)
Lines: 43

In article <13096@cup.portal.com> bcase@cup.portal.com (Brian bcase Case)
writes:

    determined by what instructions are executed, e.g., I can write a program
    that uses only the fast instructions of the upcoming re-implementations
    of popular CISCs to get the CPI down (this is, in fact, what the updated
    compilers for these micros will do), but does this make these
    architectures RISCs?

What about the idea (from the 801 project) that old S/360 architecture is
RISCy, if one uses only RR format instructions and uses RX only for loads and
stores? In most medium/large S/360 and subsequent machines, RR and RX
instruction were hardwired and RISCy in flavour indeed; 16 general purpose
registers etc... can be argued to make for a pretty RISCy machine
architecture in general. I am not sure, but probably the 801 team started
thinking of RISC by looking at the implementation of RR and RX subset of
medium/large S/360s and successors indeed.

    Perhaps some would argue yes, but realistically,
    the architecture hasn't changed, i.e., the old, slow instruction are
    still there, and they are still slow (and old :-).  Comments?

I take Patterson's 1985 CACM paper as a reasonable (generic) definition for
what is RISC; as I understand that paper, RISC is also the idea that old and
slow instructions DO affect the implementation, by lengthening the cycle time
and therefore slowing down even simple, fast ones.

One thing is RISC architecture, one is implementation indeed; however as far
as I understand it one of the essential claims of RISC advocates is that
while simple architectures may be "less efficient" under some architectural
metric than complex architectures, but they are far "more efficient" at
exploiting implementation advances, e.g. new or special technologies that are
much faster but that cannot be used for complex architectures because of low
density.

With this I agree; indeed I think it is one of the main benefits of simple
architectures, whether they exhibit most of the traditional paraphernalia of
RISCs (large caches, large register sets, multiple register windows, or
whatever else the designer of a particular RISC thinks is RISCy :->) or not
(e.g. the transputer, or even the burroughs mainframes :->).
-- 
Piercarlo "Peter" Grandi			INET: pcg@cs.aber.ac.uk
Dept of CS, UCW Aberystwyth, Wales		UUCP: ...!mcvax!ukc!aber-cs!pcg