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From: yk@a.nl.cs.cmu.edu (Yasusi Kanada)
Newsgroups: comp.arch
Subject: Chaining on IBM 3090 VF
Keywords: chaining, vector processor
Message-ID: <3950@pt.cs.cmu.edu>
Date: 2 Jan 89 15:48:38 GMT
Organization: Carnegie-Mellon University, CS/RI
Lines: 13

I read an article of IBM 3090 in 88-12 issue of Transaction of Information
Processing (written in Japanese) recently.  In this article, the author
(in IBM Tokyo Research Center) writes that the following instruction sequence
is executed in CHAINED manner, so the result is generated every cycle.

	VL	VR0,A(R1)
	VA	VR0,B(R2)
	VST	VR0,C(R3)

Is that true?  Thanks in advance.

-Yasusi Kanada

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