Path: utzoo!attcan!uunet!lll-winken!lll-lcc!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: MIPS supports 80- & 128-bit floats.
Keywords: multiple-precision floating-point, IEEE standard floating-point
Message-ID: <20295@ames.arc.nasa.gov>
Date: 5 Jan 89 17:32:59 GMT
References: <10452@obiwan.mips.COM> <325@loligo.fsu.edu>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 28

In article <325@loligo.fsu.edu> mccalpin@masig1.ocean.fsu.edu (John D. McCalpin) writes:

>There is some hesitancy in the supercomputer community to switch to the
>IEEE format because the exponent range of 64-bit numbers is so much
>smaller than the range currently provided by Cray and CDC/ETA formats.
>The IEEE 64-bit allows a range of about 1.0e-308 to 1.0e+308, while the
>Cray and CDC/ETA machines allow a range of about 1.0e-4000 to 1.0e+4000.

I have never heard of any such hesitations on the part of users, although
there may be some, about the IEEE exponent size.  Most users that I know
of would welcome having the same format on their supercomputer as on
their graphics engine (often IEEE), and the IEEE format is considered
among the best available by numerical analysts.  ("welcome" seems a little
weak in retrospect.  Some people would kill for it.   Others wouldn't
care much because they have resigned themselves to the annoyance and
performance penalties of frequent data conversion.) 

The only hesitations I have heard have been by hardware designers who don't
like handling IEEE underflow and exception requirements in deeply pipelined
machines.  However, it seems that if you accept a big penalty for the usual
unusual special cases, you can make it work just fine.


-- 
  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117