Path: utzoo!attcan!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: 100 MHz GaAs processor
Message-ID: <2013@scolex>
Date: 5 Jan 89 11:30:33 GMT
Organization: The Santa Cruz Operation, Inc.
Lines: 67

From the December 22 1988 Issue of _Electronic Design_, typed in without
permission; I haven't seen this before, but I may have missed it, so I'm
sorry if it's been mentioned.

GaAs Process Yields 32-bit, 100-MHz RISC Processor--200 MHz Next Target

Using its unique 2-micrometer heterojunction bipolar-transistor gallium-arsenide
process, Texas Instruments has demonstrated a 32-bit RISC processor that runs
at a 100-MHz clock rate.  Aimed primarily at military applications, the
12,900-gate microprocessor is the largest functional block to date built
on a GaAs substrate.

The microprocessor, which measures 440 by 415 mils, has 171 signal pins and
includes a 16-word-by-32-bit register file and a 32-bit ALU.  The six-stage
internal-pipeline architecture features a separate 32-bit data bus and a
26-bit address bus to prevent t data bottlenecks associated with multiplexed
buses.

Under a contract with the Defense Advanced Research Projects Agency (DARPA),
the processor was developed by TI's Defense Systems and Electronics Group,
of Dallas, with support from Control Data Corp.  As such, it utilized the
DARPA Microprocessor without Interlocked Pipe Stages (or MIPS) Core
Instruction Set Architecture specification, which is favored by the
Department of Defense for the next generation of standard processors.

For development support, MIPS Computer Systems supplies the DARPA ISA
translator for use on Control Data machines.  In addition, TI has an
optimizing translator, which takes the intermediate microprocessor format
form the ISA and boils it down to direct microcode.  Code can run in
external ROM or RAM.

TI plans to shrink the design by next April using a 1.5-um process.  The
goal is to achieve a sustained 200 MIPS by 1991.  Already, TI has
demonstrated the 160-ps loaded-gate delay required for 200-MHz operation by
using the company's 1.5um 6000-gate GaAs arrays.  That process is expected
to yield a 10,000-gate GaAs array by the first quarter of 1989.

Support chips are available to allow both the 100-MHz and future 200-MHz
processors to operate at a system level.  For example, the 200-MHz
processor, with its 5-ns cycle time, will require 2-ns access-time static
RAMs for no-wait-state operations.  This is achievable with 4kbit biCMOS
static RAMs, which are available from National Semiconductor and TI.
Already available for the 100-MHz operation are 16- and 64-kbit GaAs RAMs
from TI and Rockwell Semiconductor.  And for slightly slower operations, a
256-kbit 8-ns biCOMOS static RAM can be used from TI, National, or NEC.  TI
will also introduce a GaAs memory-management unit and coprocessor to round
out the family, but no time frame is specified.

To verify 100-MHz processor speed, TI used the IMS Logic Master ASIC tester,
the only system that can handle the high speeds and pin counts involved.  At
present, it is unknown how the 200-MHz version will be tested.

The 32-bit RISC processor effort is independent of another RISC processor
plan TI is working on.  That one concerns the development of a second source
for the Sun-Fujitsu Sparc 32-bit processor.
		John Gabay
--------------

Anybody know much about this thing?  Pardon my ignorance, but is this MIPS
ISA the same as the MIPSco we all know and love?  Or just something similar
and related?  Anybody actually got to *play* with one of these beasties (if
you have, you could probably make many *many* friends by sharing it 8-))?

-- 
Sean Eric Fagan  | "Merry Christmas, drive carefully and have some great sex."
seanf@sco.UUCP   |     -- Art Hoppe
(408) 458-1422   | Any opinions expressed are my own, not my employers'.