Path: utzoo!attcan!uunet!husc6!mailrus!cornell!uw-beaver!uw-june!uw-entropy!quick!srg
From: srg@quick.COM (Spencer Garrett)
Newsgroups: comp.arch
Subject: Re: 100 MHz GaAs processor
Message-ID: <296@quick.COM>
Date: 7 Jan 89 21:53:18 GMT
References: <2013@scolex>
Organization: Quicksilver Engineering, Seattle
Lines: 3

Anybody got a reference for the DARPA Microprocessor without
Interlocked Pipe Stages (or MIPS) Core Instruction Set
Architecture specification?