Path: utzoo!attcan!uunet!husc6!rutgers!rochester!pt.cs.cmu.edu!k.gp.cs.cmu.edu!lindsay
From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: MIPS CORE ISA
Message-ID: <3980@pt.cs.cmu.edu>
Date: 8 Jan 89 03:01:07 GMT
References: <2013@scolex> <296@quick.COM>
Organization: Carnegie-Mellon University, CS/RI
Lines: 27

In article <296@quick.COM> srg@quick.COM (Spencer Garrett) writes:
>Anybody got a reference for the DARPA Microprocessor without
>Interlocked Pipe Stages (or MIPS) Core Instruction Set
>Architecture specification?

My copy says
	Core Set of Assembly Language Instructions 
	for MIPS-based Microprocessors
	Version 3.2
	30 October 1987

	Maintained by
	Robert Firth
	Software Engineering Institute
	Carnegie Mellon University
	Pittsburgh
	Pennsylvania 15213-3890
	(412) 268-6305

As I understand it, MIPS Corp. uses something slightly different, which
is close enough that a mechanical translation is practical. Also,
machines which adhere to this ISA may have differing native machine
languages.  (The standardization is at the assembler level, not at the
binary level. For example, all those famous NOPs are generated at
assembly time.)
-- 
Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science
--