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From: phipps@garth.UUCP (Clay Phipps)
Newsgroups: comp.arch,comp.lang.fortran,comp.misc
Subject: Re: Quadruple-Precision Floating Point ?
Summary: CDC 128-bit floating-point was done in microcode.
Keywords: CDC,Cyber180,floating-point
Message-ID: <2303@garth.UUCP>
Date: 29 Dec 88 05:30:20 GMT
References: <8561@alice.UUCP> <3688@s.cc.purdue.edu> <285@loligo.fsu.edu> <2334@tekcae.CAX.TEK.COM>
Reply-To: phipps@garth.UUCP (Clay Phipps)
Organization: INTERGRAPH (APD) -- Palo Alto, CA
Lines: 27

In article <2334@tekcae.CAX.TEK.COM>,
kurtk@tekcae.CAX.TEK.COM (Kurt Krueger) writes:
>Lots of deleted stuff about CDC doing double precision (128 bit) floating
>arithmetic with two seperate instructions ....
>
>The new 180 series machines DO have a real full double precision 
>(128 bit) machine instruction set for the four basic arithmetic ops.

Even the top-of-the-line C180 model 99_ perform their 128-bit floating-point
operations in microcode.  The 64-bit floating-point is done in hardware.

Not exactly the choice that one would expect from a company with 
the tradition of CDC, but that's what its management decided to do.

>The interesting thing is that running that machine in the 170 mode 
>(with the FXi and DXi instructions) would slightly beat the machine 
>in the 180 mode.  Which goes to show that the mere presence of 
>128 bit instructions doesn't automatically make for speed.

I don't know whether the FXi and DXi were done in hardware;
if they were, that might have provided a sufficient edge.

-- 
[The foregoing may or may not represent the position, if any, of my employer]
 
Clay Phipps                       {ingr,pyramid,sri-unix!hplabs}!garth!phipps
Intergraph APD, 2400#4 Geng Road, Palo Alto, CA 93403            415/494-8800