Path: utzoo!attcan!uunet!portal!cup.portal.com!mslater From: mslater@cup.portal.com (Michael Z Slater) Newsgroups: comp.sys.intel Subject: Re: 80486 Message-ID: <12860@cup.portal.com> Date: 23 Dec 88 04:49:27 GMT References: <17566@vax5.CIT.CORNELL.EDU> <5800@cadnetix.COM> <316@imuse.uucp> <2582@udccvax1.acs.udel.EDU> Distribution: na Organization: The Portal System (TM) Lines: 31 > 486 rumors This is a slippery subject, but I'll venture a few items that I'm fairly confident in. o On-chip caches, 4K or so o Versions with and without on-chip floating-point o Average clocks per instruction close to 2, for a several-times speedup over the 386 o Radically different bus interface o 33 MHz initial clock rate o Announcement around April '89 We also published a detailed article speculating that it would have downloadable microcode in some form. I've heard this from enough places that I believe there is some kernel of truth to it, but I now doubt the microcode is "soft" on a wide scale. Another very interesting aspect of the 486 is the chip that will be promoted as a math coprocessor, code-named the N10. This is in fact a stand-alone RISC processor, with astounding floating-point performance: I've been told 50 MFLOPS double-precision. It will be coupled in some way with the 486, with the 486 offloading tasks to it. Whether or not it will be marketed separately is up in the air. As for faster MS-DOS machines, I'll admit to spending many hours in MS-DOS (mostly Ventura Publisher), and I'd be delighted to have an MS-DOS machine that was 4X faster than my 386 box. Michael Slater, Microprocessor Report, 550 California Ave, Suite 320, Palo Alto, CA 94306; 415/494-2677 mslater@cup.portal.com