Path: utzoo!attcan!uunet!tektronix!tekecs!bruce From: bruce@blue.gwd.tek.com (Bruce Robertson) Newsgroups: comp.sys.m68k Subject: Re: 68000 vs. 68020 question. Message-ID: Date: 3 Jan 89 18:02:16 GMT References: <322@cstw01.UUCP> Sender: nobody@tekecs.TEK.COM Organization: Tektronix ITD, Wilsonville, OR Lines: 31 In-reply-to: meulenbr@cstw01.UUCP's message of 2 Jan 89 09:15:14 GMT I've also worked with this sort of arrangement in the past, and I found that you only just break even with the cache enabled, and lose dramatically with the cache off. One thing that will cause you trouble is instructions not aligned on long word boundaries. For example, the following instruction sequence takes only two fetches with the 68000, but a total of 4 on the 68020 with 16 bit memory: 0x02: moveq #1,d0 0x04: bra.b The words at location 0x00 and 0x06 are fetched, even though they are never used. If the branch target is misaligned, you have yet another wasted fetch. Also, I can't remember this for sure, but I think the 68020 may prefetch the instruction past the branch, on the assumption that you aren't going to branch, and that's two more 16-bit accesses wasted if you *do* branch. - will the 020 start instruction execution while the second bus cycle is still in progress? I can't say for sure, but it seems extremely unlikely since it's the bus interface that is doing the dynamic bus sizing, transparently to the rest of the processor. -- -- Bruce Robertson bruce@blue.gwd.tek.com