Path: utzoo!attcan!uunet!lll-winken!lll-lcc!ames!pasteur!ucbvax!hplabs!motsj1!bjh
From: bjh@motsj1.UUCP (Brad Holtzinger)
Newsgroups: comp.sys.m68k
Subject: Re: 68000 vs. 68020 question.
Message-ID: <1312@motsj1.UUCP>
Date: 3 Jan 89 14:51:02 GMT
References: <322@cstw01.UUCP>
Reply-To: bjh@motsj1.UUCP (Brad Holtzinger)
Organization: Motorola Microcomputer Division, San Jose Ca.
Lines: 30

meulenbr@cst.UUCP writes:
>
>My questions:
>- is the above scenario a plausible explanation (the instruction used in
>  the test was a NOP).

Your choice of instructions is a poor one.  The nop instruction
in the 68020 does more than just nothing, it is also used as a
pipeline synchronizer.  All possibilities of instruction overlap
disappear when the nop is executed.  Typically the bus
control state machine would be decoupled (allowed to operate in
parallel) from the execution unit,
allowing the bus control state machine to complete the write bus cycle
of one instruction while the next instruction's execution may be
started. The next instruction would not be started if its operand
was located in a memory location.  (ie. All reads are sync points in
the 68020 microcode.)

>- will the 020 start instruction execution while the second bus cycle is
>  still in progress?

It should but your choice of instruction may negate any
measureable effect.

I hope that this is helpful.
-- 
Brad Holtzinger     Western Region Systems Engineering Manager
Motorola Microcomputer Division 
1150 Kifer Road, Sunnyvale, CA  94086, UUCP: {hplabs, mot, oakhill} !motsj1!bjh
Telephone:  +1 408-991-7340