Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!think!ames!amdcad!sun!pitstop!sundc!seismo!uunet!munnari!otc!metro!ipso!runx!betz
From: betz@runx.ips.oz (Andrew Betzis)
Newsgroups: comp.sys.mac
Subject: MACPLUS hardware question (repost)?
Message-ID: <1915@runx.ips.oz>
Date: 28 Dec 88 00:58:28 GMT
Organization: RUNX Un*x Timeshare.  Sydney, Australia.
Lines: 13


??	Has anyone had experience in interfacing to the MacPlus via the 68K? 
The problem I have is trying to have data ready by the time DTACK/ is
sampled in a normal MacPLus BUS cycle. Is there any way (without modifying
the CPU board) to delay DTACK/ so that a data transfer would take two normal
BUS cycles? Another way would be through VPA, VMA but is would take at least
three normal BUS cycles.

thanks & :-)
Andrew Betzis.

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