Path: utzoo!attcan!uunet!lll-winken!ames!mailrus!csd4.milw.wisc.edu!nic.MR.NET!umn-cs!bungia!cimcor!jim_d
From: jim_d@cimcor.mn.org (Jim Dahlberg)
Newsgroups: comp.arch
Subject: RE: 100 MHz GaAs processor
Message-ID: <635@cimcor.mn.org>
Date: 9 Jan 89 05:17:46 GMT
Organization: Grenier & friends, Forest Lake, MN
Lines: 35

I worked on the TI/CDC GaAs RISC project on the floating point chip
architecture.  Here are some answers to your questions.

>the processor was developed by TI's Defense Systems and Electronics Group,
>of Dallas, with support from Control Data Corp.

CDC designed and simulated the chip at the architectural level, and TI
did the detailed gate-level design.

>As such, it utilized the
>DARPA Microprocessor without Interlocked Pipe Stages (or MIPS) Core
>Instruction Set Architecture specification, which is favored by the

Don't confuse the DARPA Core ISA with the MIPS Incorporated R2000/R3000
ISA.  The Core ISA is not directly implemented in any hardware that I
know of.  Instead, there are *compatible* ISAs which can easily
be translated into, from the Core ISA.  For example, there is a translator
which translates a Core ISA program into R2000 code.  There is also one
that translates from Core ISA into the TI/CDC GaAs RISC code.

This allows using the same compilers with any Core ISA compatible machine.
All that needs to be written is a relatively simple translator.  I guess
you could say that the Core ISA is really just an intermediate language.
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We currently have a working demonstration board at CDC with the TI/CDC
GaAs RISC chip on it, a small amount of ECL memory, and an interface to a
PC clone.  We also shipped a demo board to TI.

There is one other DARPA sponsored GaAs RISC chip which was designed by
McDonald Douglas.  I don't know its current status.

    Jim Dahlberg
    Internet: jim_d@cimcor.mn.org
    UUCP:     uunet!rosevax!cimcor!jim_d