Path: utzoo!utgpu!watmath!clyde!att!pacbell!ames!lll-lcc!pyramid!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: 100 MHz GaAs processor
Message-ID: <5659@cbmvax.UUCP>
Date: 11 Jan 89 06:33:12 GMT
References: <2013@scolex>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 17

In article <2013@scolex> seanf@sco.COM (Sean Fagan) writes:
>GaAs Process Yields 32-bit, 100-MHz RISC Processor--200 MHz Next Target

>Anybody know much about this thing?  Pardon my ignorance, but is this MIPS
>ISA the same as the MIPSco we all know and love?  Or just something similar
>and related?  Anybody actually got to *play* with one of these beasties (if
>you have, you could probably make many *many* friends by sharing it 8-))?

	No, this is the same ISA discussed here some time back, the CORE
ISA, as used by the 40 Mips (peak) CMOS GE Rpm-40, part of the same DARPA
program.  About the only connection is that Dr Gross, who designed the
original university MIPS RISC CPU isa also designed the CORE isa.  If you want
one, talk to GE (GE sold most of it's silicon business, maybe whoever
bought it has the rights to the masks).

-- 
Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup