Path: utzoo!attcan!uunet!lll-winken!ames!oliveb!sun!chiba!khb
From: khb%chiba@Sun.COM (Keith Bierman - Sun Tactical Engineering)
Newsgroups: comp.arch
Subject: Re: Solid State Secondary Storage
Keywords: ram, wafer, disk
Message-ID: <85327@sun.uucp>
Date: 14 Jan 89 00:46:23 GMT
References: <248@vlsi.ll.mit.edu> <408@laic.UUCP> <2710@ficc.uu.net>
Sender: news@sun.uucp
Reply-To: khb@sun.UUCP (Keith Bierman - Sun Tactical Engineering)
Distribution: comp
Organization: Sun Microsystems, Mountain View
Lines: 38

In article <2710@ficc.uu.net> karl@ficc.uu.net (karl lehenbauer) writes:
>In article <408@laic.UUCP>, darin@nova.laic.uucp (Darin Johnson) writes:
>> It would make a very nice paging device.  Since decent paging devices
>> are relatively expensive (we're talking fast disks, not SCSI or
>> ST225's), this would be a nice alternative.  Think about something like
>> common LISP on a personal computer.  Currently, most do not have paging,
>> and if they did have paging it would be to a slow disk.  A device like
>> you described would vastly improve the performance.
>
>Unless you already had as much directly addressed memory as your bus could
>support, it would always be a win under a VM system to add RAM as
>bus memory rather than as a fast disk for paging use, because you'll still
>take page faults to get data from your RAM disk but you won't for the same
>data in directly addressed RAM.  

The question is cost. The orginal posting made it clear that this new
RAM would be slower, but much cheaper. Without major modifications to
the VM algorithms putting 1-3order of magnitude slower memory on the
system would produce a major slowdown.

>
>Also, support for mapped files is starting to show up (Mach, etc), the
>result being that your files logically appear in your address space and
>data is loaded from page faults.  This makes having lots of directly
>addressed RAM all the more desirable.

Cost and size are still constraints. Very high performance systems
have many levels of memory (multi-level cache, high speed ram, slower
ram (like the item under discussion) disks of various speeds, tapes,
etc. Look at very large Amdahl's or IBM's or Cray's or Fujuitsu's to
see how this works. 

For very low performance CPU's (vis a vis the memory system) one uses
one set of design considerations. For very fast CPU's (say, for
example, a 4nsec GaS RISC) multiple levels of memory becomes key to
performance design.
Keith H. Bierman
It's Not My Fault ---- I Voted for Bill & Opus