Path: utzoo!attcan!uunet!tektronix!sequent!mntgfx!mbutts From: mbutts@mntgfx.mentor.com (Mike Butts) Newsgroups: comp.arch Subject: Re: The scoop on the 80960 Message-ID: <1989Jan13.093508.251@mntgfx.mentor.com> Date: 13 Jan 89 17:35:04 GMT References: Organization: Mentor Graphics Corporation, Beaverton Oregon Lines: 25 From article , by jac@paul.rutgers.edu (Jonathan A. Chandross): > He told me that he was at Intel about five years ago and was part of a team > that designed a very powerful fault tolerant machine. The central processors > were very very CISCy and had a very parallel internal architecture. The I/O > processor chips were single chip microcoded channel controllers which were far > more powerful that the IOPs that Intel was selling at the time. > > Anyway, it seems that Intel shelved the project but decided that the processors > could be sold on the open market. However, the processors made the 80386 look > like the dinosaur it really is. This meant that the sales of the 80386 might > be "negatively impacted" (to use Pentagon speak), an obvious no-no. > > So Intel decided to cut out most of the hardware on the data path, remove any > architectural parallelism, and in general to cripple the chip in such a way > that the sales of the 80386 were safe. > Rumor around here has it that the difference between the 80960 CPU chip and the CPU chip used in the new Biin (Intel/Siemens joint venture) fault-tolerant machines is one or two bond wires on the same die. -- Mike Butts, Research Engineer KC7IT 503-626-1302 Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton OR 97005 ...!{sequent,tessi,apollo}!mntgfx!mbutts OR mbutts@pdx.MENTOR.COM These are my opinions, & not necessarily those of Mentor Graphics.