Path: utzoo!attcan!uunet!lll-winken!ames!mailrus!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Wafer Scale Floating Point chip
Keywords: silicon frisbee(tm) floating point
Message-ID: <34593@bbn.COM>
Date: 16 Jan 89 16:05:51 GMT
References: <335@belltec.UUCP>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 20

In article <335@belltec.UUCP> jom@belltec.UUCP (Jerry Merlaine) writes:
>If you want to do something useful with wafer scale technology, build
>me an IEEE floating point look-up table ROM.

I have a pair of ECL floating point chips on my desk that do DP add,sub,
and mul in under 60ns.  Lookup tables used to sound great, but
technology marches on...

Watching this discussion, it looks to me like the consensus is that the
large slow cheap RAM belongs in a level of the memory heirarchy between
conventional DRAM and conventional disk.  It was proposed to be used as
RAMdisk, particularly for paging, with the intention of getting use out
of it quickly; no new concepts were introduced, that would need OS's to
be rewritten to get full benefit.  No one wants to replace conventional
DRAM's with it, because the cache TTM would go up; it can't replace disk
as it would be volatle.

Is it time to add a new level of the memory heirarchy to systems, and do
a thorough job of defining its architecture?
-Stan