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From: mark@hubcap.UUCP (Mark Smotherman)
Newsgroups: comp.arch
Subject: Re: Synchronisation (was re: MIPS Architecture Question)
Summary: some issues appear muddled
Keywords: synchronisation, read-modify-write
Message-ID: <4124@hubcap.UUCP>
Date: 17 Jan 89 22:08:45 GMT
References: <5434@ux.cs.man.ac.uk>
Organization: Clemson University, Clemson, SC
Lines: 50

In article <5434@ux.cs.man.ac.uk>, rmd@r3.cs.man.ac.uk writes:
> ... it is possible to
> implement a TAS instruction with a sequence of simpler instructions!
> ... with support for multi-processing.
                       ^^^^^^^^^^^^^^^^
	From the article, it appears that multi-tasking on a single CPU
	is being discussed rather than multiprocessor support as was the
	apparent intent of the original MIPS Arch. Ques. posting.

> interrupt routines which could trample over this code must set the

	I'm not sure I understand why TAS would be used between ISRs
	and user processes.  If the TAS is used (ala semaphore signal) to
	unblock a (spinning) user process, then a simple store will
	suffice.  If, instead, the TAS is used to implement mutual
	exclusion between user processes and ISRs, then a deadlock seems
	to occur: i.e., if the user code holds the TAS lock and an ISR
	is invoked, then the ISR spins on the lock and cannot return
	to user code to allow release of the lock.

	Is the purpose, then, a conditional wait by low-priority ISRs to
	conditionally enter a critical section?  (i.e. the highest
	priority ISR could always assume indivisible operation and
	check the lock using separate load and compare-and-branch insts.)

	For ISR/user process mutual exclusion on a single CPU, I'm more
	familiar with disabling interrupts during user critical sections
	and low-priority ISRs.  E.g. single-processor UNIX.

	If the TAS is used for mutual exclusion between user processes,
	then a fair share scheduler must be implemented, since static
	process priorities can lead to deadlock.  Also, a blocking form
	of IPC seems more appropriate than spinning.

	I am more familiar with the use of TAS as a method of *inter-
	processor* synchronization for use by *disabled* OS code.  E.g.
	see the programming notes in IBM S/370 Princ. Ops. for TAS.
	Thus, using both interrupt disabling and TAS, one could implement,
	say, semaphore wait and signal operations for a multiprocessor.

	So, I guess I need more info on why you would want TAS for single
	CPU operation.  Am I missing something?  Do ISRs in this case
	want the equivalent of a conditional semaphore wait?

> ...  This scheme could suffer complications with operations such as DMA,

	and with mutliprocessor operation!
-- 
Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634
INTERNET: mark@hubcap.clemson.edu    UUCP: gatech!hubcap!mark