Path: utzoo!attcan!uunet!mfci!colwell
From: colwell@mfci.UUCP (Robert Colwell)
Newsgroups: comp.arch
Subject: Re: Wafer Scale Floating Point chip
Keywords: silicon frisbee(tm) floating point
Message-ID: <624@m3.mfci.UUCP>
Date: 17 Jan 89 14:14:19 GMT
References: <335@belltec.UUCP> <34593@bbn.COM>
Sender: colwell@mfci.UUCP
Reply-To: colwell@mfci.UUCP (Robert Colwell)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 26

In article <34593@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
>In article <335@belltec.UUCP> jom@belltec.UUCP (Jerry Merlaine) writes:
>>If you want to do something useful with wafer scale technology, build
>>me an IEEE floating point look-up table ROM.
>
>I have a pair of ECL floating point chips on my desk that do DP add,sub,
>and mul in under 60ns.  Lookup tables used to sound great, but
>technology marches on...

True for some floating point ops, but some decently large lookup tables
would still be awfully handy for sin, cos, exp, pow, etc.

>...
>Is it time to add a new level of the memory heirarchy to systems, and do
>a thorough job of defining its architecture?

Talk about your truly radical new ideas.  Can you imagine getting comp.arch
to come to a consensus on exactly how to tie a new memory hierarchy into
a generic computer ISA, including its control or interactions with the
compiler or compilers?  There'd be so much fur flying that the animal
rights activists would boycott everyone's computers.

Bob Colwell               ..!uunet!mfci!colwell
Multiflow Computer     or colwell@multiflow.com
175 N. Main St.
Branford, CT 06405     203-488-6090